Scaling of devices has been instrumental in the improvements in speed and power consumption of devices, e.g., transistor technologies in RF applications. As newer technology nodes are being designed, parameters such as MOSFET gate oxide thickness and the power supply voltage have also been reduced. In fact, scaling of devices has also reduced capacitances of such devices.
Although technology has progressed significantly, such evolution (scaling) of the devices is becoming increasingly more difficult. For RF FET switches which operate at AC power levels of 10's or 100's of watts, this scaling is less important due to concerns about degrading the FET breakdown. For these RF FET switches, their performance has been improved primarily by reducing the channel mobility through the use of strained films over the gate and by changing the implants and anneals used to fabricate the FETs.
To increase efficiencies, other design schemes, in addition to the use of stressed films and other process parameters, have emerged. These design schemes include SOI technologies, as well as the use of strained materials under the devices (in the channel of the device) to increase channel mobility. For example, using strained nitride films has increased the channel mobility of RF SOI NFET switches by approximately 5%. However, these strained films are very thick, e.g., on the order of 65 nm, and do not scale well to tighter ground rules in smaller technology nodes.